In general, a video signal is a low voltage signal that contains intensity information in combination with timing information, which is used to drive a display system. A video signal comprises a plurality of video frames, wherein a vertical synchronization (or Vsync) pulse is generated at the end of each video frame. Each video frame comprises a plurality of lines which contain video information that is processed for driving lines of a screen or monitor, for example.
FIG. 1 schematically illustrates an analog video signal (10), in particular, a color video burst signal (CVBS). The analog video signal (10) comprises front porch (11) portions, horizontal synchronization (Hsync) pulses (12), back porch (12) portions that contain a color burst signal (13a), and active video signal (14) portions. The Hsync pulses (12) identify the beginning of each line of video information. Each Hsync pulse (12) is preceded by a front porch (11) and terminated by a back porch (13). The color burst signal (13a) is utilized in various video formats (e.g., NTSC and PAL) as a color calibration reference. An active video signal (14) is located between the back porch (13) and the front porch (11) of a next Hsync pulse (12).
Each line of the video signal (10) begins at a falling edge of a Hsync pulse (12) and ends at a falling edge of the next Hsync pulse (12). The front porch (11) and back porch (13) are at a DC voltage level referred to as a “blanking level”, BL) (e.g., 0V), which is specified based on the given video standard. The Hsync pulses (12) have a DC voltage level (or amplitude) referred to as the “synchronization level”, SL, which has a DC level less than the BL. The falling and rising edges of an Hsync pulse (12) are defined based on a DC slice level, which is typically specified as 50% of the Hsync pulse amplitude, or SL, relative to the BL. The distance between the back porch (13) and a front porch (11) of a given line of video is a parameter that is specified based on the given video signal standard.
Various types of video processing systems and methods have been developed for processing video signals (such as depicted in FIG. 1) to extract video and timing information that is used for driving a display system. One important aspect of video processing is the ability to accurately detect the Vsync and Hsync signals for properly identifying separate frames and properly generating and displaying the line information of each video frame. FIG. 2A is a high-level block diagram that schematically illustrates a conventional video signal processing system (100). In general, the video processing system (100) comprises a Y/C separator module (110), a synchronization detector module (120) and a demodulator module (130).
The sync detector module (20) detects Hsync and Vsync of an input video signal (10). The Y/C separator (110) separates luminance Y and chrominance C signals from the input video signal (10) based on the Sync signals detected by the Sync detector (120). The demodulator (130) interpolates the extracted Y and C signals and generates video data signals (R,G,B/Y,Cb,Cr) that are further processed by a video processing unit to generate control signals for driving a display device to display a video picture.
FIG. 2B is a block diagram that schematically illustrates a conventional embodiment of the Sync detector module (120) for detecting Hsync signals of an input video signal. The detector (120) comprises a slicer module (121), a slice level generator (122), a phase detector (123), and a PLL (phase-locked loop) (124), which all operate under control of a controller (125). In general, the slicer (121) detects the rising and falling edges of Hsync signals in the input video signal (10) based on a DC slice level that is generated by the slice level generator (122). The slice level generator (122) processes the input video signal (10) to determine a DC slice level using known techniques. For instance, a DC slice level can be determined based on a priori knowledge of the DC amplitudes, transitions, and structures of various portions of the input video signal. A DC slice level can be determined based on estimates of relative amplitudes between the SL of the Hsync pulse and other levels such as BL or the peak of the active video portions.
Based on the DC slice level determined by the slice level generator (122), the slicer module (121) will detect the falling edges of Hsync pulses (12) in the video signal (10) at points where the input video signal level moves below the determined DC slice level. Similarly, the slicer module (121) will detect the rising edges of Hsync pulses (12) in the video signal (10) at points where the input video signal level moves above the determined DC slice level.
The PLL (124) operates to generate and output control pulses (Hsync) that are synchronized to the detected Hsync pulses in the input video signal (10). The phase detector (123) determines an amount of phase difference between the Hsync pulses extracted from the video signal (10) by the slicer (121) and the Sync pulses generated and output from the PLL (124). The phase detector (123) will generate a control signal based on the detected phase difference, which causes the PLL (124) to perform error correction to adjust the output Sync pulses to be phase aligned to the extracted Hsync pulses.
Depending on the type of Hsync detections employed, the conventional system of FIGS. 2A/2B can exhibit degraded performance due to decreased Hsync detection accuracy. In particular, for Hsync detection methods that are based on comparing the DC levels of the video signal to known or determined threshold amplitudes (e.g., BL, SL, etc.), accurate detection of the HSync may not be possible when the video signal is noisy. In addition, the transmission of a video signal can lead to distortion or loss of the DC levels of the input video signal, thus, making is difficult or impossible to detect the Hsync pulses.